WRMFRZ=0, MRP=0, RRS=0, EACEN=0
Control 2 register
EACEN | Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes 0 (0): Rx Mailbox filter’s IDE bit is always compared and RTR is never compared despite mask bits. 1 (1): Enables the comparison of both Rx Mailbox filter’s IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. |
RRS | Remote Request Storing 0 (0): Remote Response Frame is generated. 1 (1): Remote Request Frame is stored. |
MRP | Mailboxes Reception Priority 0 (0): Matching starts from Rx FIFO and continues on Mailboxes. 1 (1): Matching starts from Mailboxes and continues on Rx FIFO. |
TASD | Tx Arbitration Start Delay |
RFFN | Number Of Rx FIFO Filters |
WRMFRZ | Write-Access To Memory In Freeze Mode 0 (0): Maintain the write access restrictions. 1 (1): Enable unrestricted write access to FlexCAN memory. |